1. The Field of the Invention
The present invention relates to the field of modem communications between a host computer, and an attached modem, across networks. More specifically the invention relates to a high throughput interface between a modem""s Digital Signal Processor (DSP) and a computer""s internal Universal Asynchronous Receiver Transmitter (UART) interface.
2. The Relevant Technology
The demands of recent software and hardware enhancements upon computer communication technology require changes to the standard hardware configuration. One computer component device that traditionally lags behind other computer system enhancements is the serial port modem interface on the personal computer. The first modems were in an external box linked to the computer via a serial cable connection. The external modem converted the serial information into analog modules for transmission across the phone lines. In this configuration, there was generally some type of UART inside of the serial port on the computer and the serial port of the modem. The computer UART would take parallel information, serialize it, and then send it across the serial cable. The modem UART would then translate information so that the modem could modulate the information for transmission. In the case of modern internal modems and PCMCIA modems, serial connection cables are not utilized, creating faster modem communication. Unfortunately, a substantial amount of legacy software expects the original UART configuration to convert the parallel data into serial data strands. This unnecessary hardware device is often blamed as the bottleneck for data transfers and the source of poor computer response. Typically, the computer user will notice substantial lag time from the computer""s central processing unit (CPU) whenever the CPU attempts to service interrupt requests involving large data transfer operations with the UART. On the other side of the local communications link, the DSP of the modern modem is also severely overburdened. Servicing multiple interrupts from the UART can drastically affect the performance and effectiveness of the DSP.
Today, the minimum serial port interface device that any modem modem should use is a 16550 UART. Lower speed devices like the 8250 UART and 16450 UART cannot operate at the speeds dictated by modem modem standards without risking data overrun errors. An overrun error occurs when a new character is received before the old character has been fetched by the computer. Once this occurs the old character is lost and unavailable for processing by the personal computer.
The original UART chip shipped with the IBM(copyright) personal computer was the 8250 UART. The 8250 UART chip was limited to a maximum data transfer rate of 9600 bits per second (bps). This chip was later replaced with the 16540 UART chip which had the same architecture as the 8250 UART; but a higher maximum bps specification. Both of these chips only had a one byte buffer. Since each character is designated by eight bits, the buffer on the 8250 UART and 16540 UART corresponded to one character. Under the DOS platform, the one byte buffer of the 8250 and 16540 UARTs provided satisfactory performance for the communication ports operating at speeds of lower than 9600 bps.
Computer designers developed the UART chips to function at 9600 bps because this speed corresponded with the performance requirements found in the underlying Microsoft(copyright) specification for the DOS systems shipped with the original IBM personal computers. A closer look at the Microsoft DOS timing specifications reveals that an interrupt was not to be disabled for more than one millisecond at a time. While an interrupt is disabled the CPU will not process send/receive requests with the communications port. Because a 9600 bps modem will deliver a character approximately every millisecond, the one byte buffer on the UART chips was sufficient to prevent data over-run errors.
This changed under the new multi-tasking Windows 3.1 operating system. There is no longer an imposed restriction on the interrupt response control as previously existed under the DOS timing specification. As a result, interrupts could be ignored longer and repeated interrupts could be handled faster. To prevent over-run errors, the 16540 UART architecture was limited to operating between 1200 and 2400 bps under the Windows operating system. This was unsatisfactory because the new modems were capable of much higher transfer rates. A serial communications port needed to operate at transfer rates of at least 38,400 bps to keep up with the faster modems. But once data transfer rates climb above 9600 bps, then the device can receive a new character before the old one has been fetched by the interrupt service routine.
When the older 8250 and 16540 UART devices were forced to perform at higher speeds, their one character buffers guaranteed over-run errors. To fix this problem, the 16550 UART was developed. It had a 16 byte buffer and was able to operate under the high demand of the new multi-tasking Windows 3.1 system. Modem modems are moving even faster with some operating at 115,200 bps. Thus, a system of buffering is required to prevent over-run errors. For example, a 16 byte buffer may not sound like a huge improvement over the 1 byte buffer, but this allows 16 characters to be received before the computer needs to service the UART data interrupt thereby increasing the maximum data transfer rate that the computer can process reliably, without risk of an over-run error, from 9600 to 153,000 bps if the processor employs a one millisecond interrupt dead time. Obviously, a 32 byte buffer, as found in the 16650 UART, increases the maximum datatransfer rate to over 300,000 bps. Unfortunately, the DOS specification which required a one millisecond maximum interrupt dead time is ignored by Windows 3.1. This means that the dead times become so severe that even speeds of 2400 bps will often result in lost characters and over-runs if using a slower processor.
A secondary benefit to increasing the buffer size over the original 1 byte is that the computer only needs to service the interrupt about 8%-12% of the time. This allows the CPU time for updating the screen or doing other computational chores, thus the computer appears more responsive. But, as the computers get faster, even the 16 and 32 byte standards are becoming ineffective and inefficient
Traditionally, the DSP would send an interrupt signal to the UART that would then be passed on to the personal computer telling the computer that data was waiting for it to pick up. Due to the slow transfer rate, the computer could function normally since it could easily handle the interrupt and return to performing its previous program function without any noticeable delay to the user. With new high speed data transfers, the modem DSP is continually waiting for the computer to send or receive more data creating more interrupts and therefore interfering with the overall performance of the personal computer. Thus the interrupt service time of the DSP to UART interface remains a critical feature to the overall performance of the computer. Also the dramatic increase in a modem""s transmission capability has created a unique problem for modems, because they must be able to increase the throughput to the computer data bus while maintaining the standard serial protocols associated with UART devices.
Unfortunately, this type of serial connection creates a tremendous overhead burden on the DSP and internal CPU handling the Input/Output Interface. The UART is forced to make several requests for character echo, parity strip, and parity add functions each requiring the DSP to virtually stop work on other projects while the data request is being transferred. What is needed is an intermediate device which can handle the simple flow control functions without hands on supervision by the DSP. More specifically, what is needed is a simple yet reliable hardware solution integrated into the modem which allows for connectivity between the DSP and the portable personal computer at a low cost. This hardware should support the widely available communication software that conforms to the accepted IEEE standards, and should also permit data communication across a conventional telephone network.
An object of the invention is to improve the throughput of a UART to DSP interface and relieve the overhead associated with servicing modem interrupts without losing compatibility with standard UART protocols, especially when performing data transfer operations.
An additional object is to provide the DSP with an efficient method to check and set status flags for various data transfer operations.
Another object is to carry out hardware echo functionality within the hardware interface without excessive DSP involvement.
A further object of the invention is to generate and remove parity from data being transmitted through the hardware interface.
Yet another object is to pace the transfer of data from the UART to the DSP by alternatively bursting and halting data transfers.
Still another object of the invention is to emulate data being serialized through a shift register at a rate established by the DSP while maintaining the advantages of parallel data transfers.
Additional objects, advantages, and novel features of the invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
In accordance with the present invention, a high throughput UART to DSP dual buffer interface includes a UART compatible module attached to a computer""s data bus. This UART compatible module being responsive to standard serial communication port commands but connected to a secondary UART to DSP Interface (UDIF) with a parallel data bus. The UART compatible module comprising a block of registers, a control block, two dedicated FIFO buffers to store data. Typically a plurality of standard UART registers includes a scratchpad register (SCR), a modem status register (MSR), a interrupt enable register (IER), a FIFO control register (FCR), a transmit hold register (THR), a modem control register (MCR), a line control register (LCR), a divisor latch low (DLL), a divisor latch high (DLM), an interrupt identification register (IIR), and a receive line status register (LSR). The UART FIFO buffers being optimized for interaction with the computer""s data processing units and data bus. One buffer being dedicated to data transmission and the other being devoted to data reception. The secondary UDIF comprising a block of registers, a flow control block, and two dedicated FIFO buffers. These buffers also being optimized, with the optimization focusing on interaction with the digital signal processor (DSP) of the modem.
The DSP is generally not bound by the buffer size constraints legacy software places on the UART and the DSP is more efficient than the host microprocessor in transmitting and receiving data. As a result, the UDIF FIFO buffers are designed larger than those found on the UART compatible module. Larger UART FIFO buffers would not always be efficiently utilized because of artificial buffer size constraints imposed by software. While both the DSP and the UART benefit from an increase in the UDIF FIFO buffers. Another method of optimization involves establishing threshold values within the buffer to alert the DSP when a buffer needs to be filled or emptied. These threshold values should be selected using a method based on the functionality and performance specifications of the DSP and the UART. Care should be taken to minimize the number of processor interrupts, while maximizing the DSP processor data throughput. One additional optimization involves maintaining a FIFO Fill Level Register containing the number of characters stored in the FIFO. This value allows the DSP to avoid checking the FIFO empty flag/FIFO full flag after every data transfer. For large data transfers, this register will reduce the number of DSP operations by 50% to 80%. Without the FIFO Fill Level register, the DSP may execute 2 to 5 times as many instructions per byte transferred. The DSP overhead savings increases according to the size of the data block being transferred. This scenario occurs frequently in the dual FIFO buffering system, because one of the objects of the system is to promote large data block transfers. Thus in utilizing a dual buffering system, the interface can create an optimized and efficient throughput system for both the computer and the modem.
Preferably, the compatible UART module is connected to the computer bus with a bidirectional parallel data interface. While the buffers of the UART compatible module and the UDIF buffers are directional, dedicated parallel data bus lines. The significance of these parallel data bus lines revolves around the nature of the serial modem connection. The computer is expecting the data to be processed in a serial fashion, but throughput can be enhanced by making the transfers across the parallel buses. Advantageously, the modem can actually encode data so that when one bit is sent across the phone line it may represent several data clusters. Under these encapsulation schemes it is important for the DSP to have larger quantities of data available than can be created serially.
In accord with one aspect of the invention, the UDIF registers and control blocks may be enabled to perform the hardware echo function, which returns characters that have just been received from the UART compatible module. Hardware echo is an important function because it allows the user to see which characters are being sent across the phone line. Thus a hardware implementation of this mode advantageously reduces the overhead on the DSP because it no longer has to redirect the data back to the computer and can focus on encoding the data for transmission.
As another aspect, the UDIF registers may be enabled to generate parity for data being sent and to remove parity from data being received. While the best mode requires a 7-bit word length be enabled for parity generation to be downloaded from the DSP, it is not the only configuration possible. It is anticipated that the device can function even when the word length varies along the standard settings of 4-bit, 5-bit, 6-bit, 7-bit, or 8-bit word lengths. Furthermore, the parity produced can be even, odd, mark, space, or no parity.
For greatest optimization, the UDIF controls the pacing of data transfers by alternatively bursting and halting data transfers to emulate data being serialized through a shift register at a rate dictated by a divisor latch value. The size of the available data burst is indicated by a UDIF register called a pacing burst count register. The length of the data transfer delay is similarly calculated using a UDIF register called a pacing wait count register. Additional hardware flow control mechanisms are employed by the UDIF to increase the throughput rates and reduce the computational overhead on the DSP, while maintaining UART compatibility. One of these flow control mechanisms includes detecting modem escape sequences and completing the sequence with a lessened DSP involvement. Several of these attention (AT) and communication commands can be be preformed by the UDIF to relieve the DSP of the overhead necessary to service the interrupt or preform the function.
The preferred embodiment of the UART to DSP Interface (UDIF) contains Several interface bus lines and various design registers, modules and timing blocks. The buses include a Tx Data Input Bus that receives data blocks from the UART, a Rx Data Output Bus that sends data blocks to the UART, a bidirectional DSP Interface Bus that sends data blocks and control signals to the DSP and receives data blocks and control signals from the DSP, and a control line bus for communication between the interface and the UART.
The UDIF memory blocks include the two FIFO blocks, presently implemented using 128xc3x978 two port memory modules. The Tx FIFO and Rx FIFO memory block store data in 8 bit character blocks, but it is envisioned that the data block size could vary from one byte to 512 bytes according to the system data size. Characters are stored in the Tx FIFO in the order that the characters are transmitted to the Tx FIFO from the UART. The Rx FIFO memory block stores characters in the order the characters are received from the DSP. Closely associated with the two aforementioned FIFO buffers are the Tx FIFO Register and Rx FIFO Register. From the DSP side, the Tx FIFO Register is read only, but it is also electronically attached to the Tx FIFO memory block. Once the DSP reads the Tx FIFO Register, the Tx FIFO Register writes the oldest character from the Tx FIFO over it previous value. The Rx FIFO Register is similar except that it is write-only from the DSP Interface side. And like the Tx FIFO Register, the Rx FIFO Register is also electronically attached to the Rx FIFO memory block except that the Rx FIFO Register writes a character to the newest character slot in the Rx FIFO each time the DSP writes data to the Rx FIFO Register. A quasi memory block found in the preferred embodiment is a sixteen bit general purpose register called the UART Scratch Register (USCR). While the USCR can be read from the UDIF interface with the DSP, the USCR actually resides on the UART side of the interface. The USCR can be used to pass data directly between the host computer and the DSP.
The UDIF provides several control and status registers for the DSP. One of the significant control and monitoring registers provided by the UDIF is the UDIF Modem Control Register (UMCR). The UMCR combines some signals that connect to the UART""s MSR, signals that control the setting of some bits in the UART""s LSR and a couple of signals that enable functions in the UDIF. In the preferred embodiment this register is an 8-bit register format for easy access by the DSP, but as with any component in this design, the size of the register could be increased or decreased to better optimize the interface with a specific DSP. The bit flags represented in the UMCR include the Parity On (PON) flag that when set conditionally activates a UDIF parity generation module that adds parity to all data blocks before they enter the Tx FIFO and a UDIF parity strip module that removes parity from all data blocks sent to said Rx Data Output.
The Echo On (EON) flag is another bit that when set, conditionally activates a UDIF hardware echo module that routes characters, after performing any parity stripping if it is enabled, from the Tx Data Input bus to the Rx Data Output bus as well as sending the characters to the Tx FIFO. The Data Carrier Detect (DCD) flag is a bit that sets or clears bit 7 of the modem status register (MSR) on a standard UART. Another flag bit attached to the MSR is the Ring Indicator (RI) bit. The RI conditionally activates or deactivates bit 6 of the MSR on the attached UART. The Data Set Ready (DSR) bit is another flag bit connected to the MSR on the attached UART, it conditionally activates bit 5 of the MSR. Finally, the Clear to Send (CTS) bit conditionally activates bit 4 of the MSR on the UART. A smaller string of self clearing bits can also be found in the data stored by the UMCR. These bits are self clearing because, writing to the location does not set the register value. Therefore there is nothing to read, so that a read of these bits will always result in a zero being read. The first of these self clearing bits is the Set Break Interrupt (SBI) bit that activates a Break Interrupt bit in the UART LSR. The second self clearing bit is the Set Rx Overrun (SRO) bit that activates the Overrun Error bit in the UART Receiver Line Status Register (LSR).
A second significant control register in the UDIF embodiment is the UDIF FIFO Control Register (UFCR). The UFCR contains status flag bits in a single register that allow the DSP to control both the Tx FIFO and the Rx FIFO. When the Transfer Disable (TDS) bit is set, it disables data transfers between the UDIF module and the UART module. The Tx FIFO Reset (TFR) bit is a self clearing bit that clears the contents of the Tx FIFO when the bit is set. Similarly, the Rx FIFO Reset (RFR) bit is another self clearing bit that clears the contents of the Rx FIFO when set.
Another important status register is the sixteen bit Divisor Latch (DIVL) register. The DIVL contains the sixteen bit Divisor value from the UART. The DSP can read the DIVL register and determine what the appropriate pacing values should be and set them. Once the DSP has made this calculation, it writes a sixteen bit value to the Character Pacing Count Register (CPCR). This value represents a data block character transfer time period and is used to pace data flow in both the Rx and Tx directions. A related sixteen bit Pacing Burst Count Register (PBCR) contains a value that indicates the number of characters that should be transferred during a data burst before halting the data transfer for both the Tx and Rx directions. Similarly, a sixteen bit Pacing Wait Count Register (PWCR) contains a value representing the number of data block   character transfer time periods during which data transfers are halted in both the Tx and Rx directions. While the actual bursting and halting functions do not have to coincide for the Tx and Rx data lines, they must share be the same length. In another pacing related register, a Tx Stale Count Register (TSCR) contains a sixteen bit stale counter value representing inactive character transfer time periods that may occur before a stale time-out interrupt will be sent to the DSP. If there is at least one character in the Tx FIFO and a TSCR +1 number of character times elapse while there were no accesses to the Tx FIFO, then the UDIF will send a stale time-out interrupt to the DSP.
An important UDIF status register is the 8 bit read only Frequently Updated Status Register (FUSR). This register contains bits that frequently change, in particular it provides 11 status signals for the Rx FIFO, the Tx FIFO, and the Request To Send (RTS) signal from the UART""s MCR bit 1. The Tx Character Time-out (TCT) bit is set when no characters have been removed from or input in to the Tx FIFO for a time period equivalent to the value in the TSCR and the FIFO contains at least one character. The TCT bit is cleared by reading the Tx FIFO. The Tx FIFO Full (TFF) bit is set when the Tx FIFO is full and zero when the Tx is not fill. The Tx FIFO Threshold (TFT) bit is set when the number of characters in the Tx FIFO is greater than the threshold value and zero when the number of data blocks in the Tx FIFO is less than or equal to the threshold value. The Tx FIFO Empty (TFE) bit is set when the Tx FIFO is empty and zero when the Tx FIFO is not empty. The Rx FIFO Full (RFF) bit is set when the Rx FIFO is full and zero when the Rx is not full. The Rx FIFO Threshold (RFT) bit is set when the number of data blocks in the Rx FIFO is less than or equal to the threshold value and zero when the number of characters in the Rx FIFO is greater than the threshold value. Finally, the Rx FIFO Empty (RFE) bit is set to indicate when the Rx FIFO is empty and zero when the Rx FIFO is not empty.
Another important feature of the preferred embodiment is knowing the fill level of the Rx FIFO and Tx FIFO. This enables the DSP to empty or fill the respective FIFO with less overhead than a standard interface. One of these registers is the read only Rx FIFO Fill Level Register (RFFL) that contains an 8-bit value representing the number of characters in the Rx FIFO. The RFFL is cleared when the Rx FIFO is reset. Similarly, the read only Tx FIFO Fill Level Register (TFFL) contains an 8-bit value representing the number of characters in the Tx FIFO. The TFFL is cleared when the Tx FIFO is reset.
Two of the most valuable registers in the preferred embodiment are the Rx FIFO Threshold Register (RFTR) and the Tx FIFO Threshold Register (TFTR). These registers allow the DSP to optimize the efficiency of the UDIF FIFO buffers in the Tx and Rx directions. The DSP can set the threshold value by writing an eight value to either the RFTR or TFTR. This value is important because it tells the UDIF how often the DSP wants to be interrupted and how long a transfer with the UART should occur before emptying or filling the UDIF Tx FIFO and Rx FIFO. By adjusting the RFTR and TFTR, the DSP can optimize its throughput levels.
The Rarely Updated Status Register (RUSR) is a non-destructive 16-bit read only status register containing bits that rarely change. The lower half of the register echoes signals from the UART""s Modem Control Register (NCR), Line Control Register (LCR), and FIFO Control Register (FCR). The signals from the LCR include the Stick Parity Select (SPS) bit that displays the value of bit 5 of the UART LCR, the Even Parity Select (EPS) bit that displays the value of bit 4 of the UART LCR, the Parity Enable (PEN) bit that displays the value of bit 3 of the UART LCR, the Set Break (SB) bit that displays the value of bit 6 in the UART LCR, and a 2 bit Word Length String (WLS) used to indicate the selected word length by displaying the value of bit 0 and bit 1 of the UART LCR. The signal from the MCR is the Data Terminal Ready (DTR) bit that displays the value of bit 0 in the MCR. The FCR signal is the UART FIFO Enable (UFE) bit that displays the value of bit 0 of the UART FCR.
The upper eight bits of the RUSR represent signals from registers set whenever a change has been made in the respective register. For example, the Delta Scratch Register (SCR) bit indicates that a write occurred to the UART Scratch Register by a Host Microprocessor. The Delta Divisor Latch Register (DIVL) bit indicates when the UART Divisor Latch Register is written to by said Host Microprocessor. The Delta Set Break (SB) bit indicates a change in the Set Break flag. The Delta Data Terminal Ready (DTR) bit indicates a change in the Data Terminal Ready flag. The Delta Uart FIFO Enable (UFE) bit indicating a change in the UFE flag.
Another method of accessing the RUSR is through the destructive sixteen bit read only Rarely Updated Status Register (RUSRclr). When the DSP reads this address location it is the same as reading the RUSR except that the read clears the delta bit flags in the upper bits of the register following the read. Specifically, the delta bits DIVL, UPS, SB, DTR, and UFE are reset.
Finally, if any of the Delta bits in the RUSR are set, the UDIF can write to the Status Interrupt Enable Register (SIER) to set several Interrupts to the DSP at once. The USCR Interrupt Enable bit enables an interrupt to the DSP when new material is waiting in the SCR. The DIVL Interrupt Enable bit enables an interrupt to the DSP when a new transfer rate value is waiting in the UART DIVL. The UPS Interrupt Enable bit enables an interrupt to the DSP when there is a change in the parity settings or in the word length settings. The SB Interrupt Enable bit enables an interrupt to the DSP when there is a change in the SB flag. The DTR Interrupt Enable bit enables an interrupt to the DSP when there is a change in the DTR flag. The UFE Interrupt Enable bit enables an interrupt to the DSP when there is a change in the UFE flag. This register is very important as it provides the UDIF with the ability to determine which of the delta bits will affect the interrupt and improve the DSP efficiency.
The high throughput UART to DSP interface thus minimizes the number of times that a modem processor and a computer processor need to be interrupted to service data transfers. In fact, many of the functions previously accomplished through a software implementation can now be more efficiently completed with the hardware interface. These commands include parity generation and removal, hardware echo, data transfer pacing, recognition and completion of escape commands, AT commands, and basic flow control commands. The parallel nature of the data transfer ensures that the transfer between modem and computer occurs in less time that a serial transfer would require, but the hardware pacing ensures that the transfer appears to function like a serialized transfer to the computer. Thereby creating compatibility with legacy software expecting serial communication.
Still other advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein the preferred embodiment is shown and described, simply by way of illustration of the best mode contemplated by the inventors in carrying out the invention. As will be realized, the invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.